Supplier: Embedded Logic Solutions
12 February, 2008
The ARM® Cortex™-M3 processor features the ARM CoreSight™ debug and trace technology that significantly expands the features of the classic Embedded ICE® on-chip debugging block. In addition to normal run-control debugging, CoreSight technology provides on-thefly memory access, data trace, event trace, and instrumentation trace via a standard low-cost JTAG connector.
Before the introduction of on-chip debugging, most software developers were using expensive In-Circuit Emulators (ICE) for application testing on microcontrollers. High-end emulators were connected via complex adapters, and offered also extensive instruction and data trace capabilities with complex triggers. These emulators were based on special bond-out devices that were different from the standard production devices and therefore very expensive compared to the actual MCU device. Modern microcontrollers run at high clock rates and come in tiny, high-pin count packages making traditional ICE technology impossible to adapt.
Today’s microcontrollers offer on-chip debug logic that gives controlled access to memory, CPU registers, and program execution. This on-chip debug logic is part of every production device and, to avoid extra chip costs, is limited in complexity. Since it is mostly accessed using a standard JTAG interface, the additional bandwidth required for instruction trace is not available. Most on-chip debug implementations provide only simple runcontrol debugging with limited breakpoint features. Cortex-M3 processor-based microcontrollers, however, integrate ARM CoreSight debug technology that provides useful trace information via a standard JTAG connector and without the need for costly hardware.
ARM On-Chip Debug Technology
With the introduction of the ARM7TDMI processor ARM provided the onchip Embedded ICE debug solution. Embedded ICE is a low-cost hardware block that provides complete run-control with two hardware break registers that can trigger either on program execution or memory access. An additional Debug Communication Channel (DCC) allows data exchange with the user application during program execution. The Embedded ICE is the standard debug unit for all ARM7 and ARM9 processor-based microcontrollers that are available today from many silicon vendors.
Since the Embedded ICE on-chip debug hardware does not provide any data or instruction trace, some ARM processor-based microcontrollers also integrate the Embedded Trace Macrocell™ (ETM™). However the high data bandwidth used by an instruction trace requires data output lines, in addition to those of the standard JTAG pins. A special ETM emulator connects to these ETM data output lines and interprets the trace information. In microcontrollers, ETM often shares useful I/O lines that are required by the user application and therefore engineers frequently cannot use the ETM unit. To minimize the I/O pins required for debugging, the new CoreSight solution provides additional operating modes via a standard JTAG connector.
CoreSight is the debug technology used in Cortex-M3 processor-based microcontrollers. A low-cost JTAG adapter (for example the Keil ULINK2) is all that is required to interface to the CoreSight on-chip debug unit. In addition to the trace features, the CoreSight unit implements additional break registers and provides on-the-fly memory access during program
execution without additional software overhead.
ARM processor-based microcontrollers are widely supported by the development tool industry. For example the ARM RealView® Microcontroller Development Kit (MDK) available from ARM/Keil provides device-specific support for more than 260 standard microcontrollers. It combines the ARM RealView Compiler with the µVision Debugger/IDE and the RTX RTOS Kernel. The µVision Debugger connects to a Cortex-M3 processor-based microcontroller using the ULINK2 USB-JTAG Adapter. ULINK2 allows Flash programming and hardware debugging and supports all operating modes of the CoreSight on-chip debug unit. The µVision debugger can display memory content and variables in several familiar formats. Even during program execution the memory and variables are permanently updated which gives the user an instant view of the current program status. It is possible to set breakpoints that trigger on specific variable accesses with or without a value.
ULINK2 can be configured to use the SWV output pin. In this mode the user can obtain trace information about:
• Data read and write of selected variables (optionally with timestamps and PC values) may be reviewed in a Logic Analyzer window.
• Event counters that show CPU cycle statistics which indicate required wait states or the idle time of the device.
• Exception and Interrupt execution with timing statistics that helps optimize interrupt functions.
• Periodic samples of the program counter that identify the location where the program is running in an endless loop.
• User trace data that can output via 32 ITM (Instrumentation Trace Macrocell) registers and may be used for timing analysis or simple printf-style debugging.
The SWV mode is non-intrusive and does not require any monitor software or additional CPU wait cycles. To reduce bandwidth for trace information, the data capturing can be selectively enabled. The trace data captured can be reviewed in the µVision Trace Records window which provides additional data display filters.
Logic Analyzer View of Variable Trace
The integrated µVision Logic Analyzer displays value changes of up to four selected variables over time. This enables changes of any global or static variable including struct members to be reviewed. When PC samples are included in the trace information the button Code Show opens the source code that creates the variable modification.
The Cortex-M3 processor provides execution statistics that help you to determine the performance of the hardware and software implementation.
The ITM unit implements 32 stimulus registers that enable additional trace data to be output via the SWV output pin.
Exception and Interrupt Trace
By enabling Exception Tracing, SWV outputs information about interrupt routine execution in the application.
The SWV trace information can be selectively enabled with a configuration dialog. Selective trace output provides the information required to analyze the actual problem and reduces the bandwidth required. The CoreSight technology therefore fulfills the requirements for MCU software development by providing complete debug and trace connection with only three I/O pins.