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Checking interconnections without test pins using JTAG Technologies

Supplier: ProDigitek By: Vincent Stafrace
20 October, 2012

JTAG Technologies introduce the JTAG Live range of tools. Simple and effective, these tools are the equivalent of an ohm meter, oscilloscope or signal generator to allow testing of pins and interconnectivity where leads and probes cannot go or have access to.

Once the assembly of a prototype or final product is complete, you want to know as quickly as possible whether the circuit is working correctly. The power supply is connected and you wait with suspense what is going to happen. A prototype usually does not work the first time or perhaps works only partially. Where is the problem, is it the design or is it because a few parts aren't mounted correctly?

Quite quickly you will reach for an oscilloscope or multimeter to verify whether the signals are correct or to check the connections between parts. These days, with multilayer boards containing finepitch and/or BGA components this is practically impossible however. So how can you test these boards?

A frequently used method is a functional test. Using special software test-routines the functionality of the board is examined. An important prerequisite of this is that the core of the circuit is functional; if it is not, then you cannot proceed with a functional test. Diagnosing the actual fault using a functional test can be difficult.

For example, the test may indicate that there is a problem with the memory section, but you don't know which pin specifically is causing the problem. 

You can also choose to do a structural test. If all the components on the circuit board are correctly interconnected, then the circuit has to work, unless there is a fault in the design. This approach makes the assumption that all the components used are okay. In other words: the objective is to demonstrate that all components are soldered correctly. The simplest method is to use a multimeter to carry out a continuity test between all components (see Figure 1).

The main advantage of such a structural test is that the exact locationof the problem will be known. A pin that's not soldered properly or is shorted to another pin is immediately discovered. In order to obtain substantial test coverage and to be able to arrive at the correct diagnosis it is necessary to test a large number of points. For this purpose, test pads are often added to the board. However, test pads cost money and require space.

So modern designs with high component density have an immediate problem. On a multilayer-board with fine-pitch or BGA components there is no room for test pins. Even worse, test pins can easily create a short between component pins (Figure 2).

The Boundary Scan architecture

Take a microcontroller as an example. In addition to the core, which provides the actual functionality of the chip, the silicon also accommodates the necessary hardware for Bscan. This additional hard-ware consists of, among others, a Bypass, an Instruction and a Boundary Scan register and a controller.

The Bscan register (BSR) is formed from transparent cells sitting between the connection pins and the core. There are also a few additional pins: TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select) and optionally TRST (Test Reset ), see Figure 3.

Figure 3. Additional hardware is integrated into a Bscan chip. This comprises, among others, an Instruction- and a Boundary Scan register and a controller.  Synchronous with the clock on TCK, bits can be shifted in via TDI and bits then exit via TDO. The actual path that these bits take is determined by clocking a specific command into the controller via TMS. There are commands to insert the Bypass-, Instruction- or BSR register in the TDI-TDO path.

The TDI-, TDO-, TMS-, TCK- and TRST-pins collectively form the Test Access Port (TAP), known to many as the JTAG interface. A large number of components already contains this JTAG interface and is by default suitable for the application of Bscan.

How does Boundary Scan work?

By inserting the BSR into the TDI-TDO path, any arbitrary bit pattern can be shifted into the Bscan cells via the TDI pin. By issuing an 'Update' the data in the BSR is copied to the connection pins. In the opposite manner, the 'Capture' instruction reads the data at the connection pins and copies it into the BSR. The contents of the BSR can then be shifted out via TDO. These two actions of 'driving' and 'sensing' are used to test the connections between components.

Example 1 By connecting the TDI of one Bscan chip to the TDO of another one, a Bscan chain is formed. To ensure correct synchronisation the TCKand TMS signals of the TAP are directly connected to each chip individually (see Figure 4). In principle, an unlimited number of Bscan components can be joined to form the chain. However, for practical reasons this is usually limited to about 10 Bscan components.

Figure 4 makes the assumption of a chain of two Bscan components,a microcontroller and an FPGA. This chain comprises the Bscan cells of IC1 plus the Bscan cells of IC2. According to the schematic,  IC1 and IC2 are connected to each other via interconnects Net_1 through Net_5.

The question is to verify whether this is actually the case on the circuit board. In other words: we have to check whether the connecting pins of IC1 and IC2 are soldered correctly and that there are no open circuits or short circuits between them. Behind each pin that is connected to Net_1 – Net_5 there is a corresponding Bscan cell. These are the cells that will be used to test the connections.

The first step is to put the combined chain in the TDI-TDO path. After that, an appropriate vector is shifted into the BSR so that the Bscan cells of IC1 that belong to Net_1–Net_5 contain logic ones. Note that while the shifting is taking place the actual state of the pins does not change. Only the moment after an 'Update' is this data in the Bscan cells applied to the connecting pins. The vector out. Software is then used to compare the vector obtained with the vector that was expected.

The latter has to be '11111', however the vector read back is '11011'. The bit that was read for Net_3 is a '0', while a '1' was expected. This indicates that there is a problem with Net_3. By using a number of clever test vectors it is possible to diagnose that there is an open circuit under the connecting pin of IC2.

In this manner it is possible to quickly locate open circuits, short circuits between individual nets and short circuits to Vcc or Gnd. In this example we assume only five connections, in practice there will easily be several tens to hundreds of connections that can be tested in this way.

This example explained how the connections between Bscan components can be tested. In this framework it is important to note that this method also works with components that comply with the IEEE1149.1 Boundary-scan standard (Bscan compliant). The average board, in addition to one or more Bscan compliant chips also contains a large number of other components such as resistors, RAM, flash memory, I/O, connectors, etc. It is possible to use Bscan for these as well.

Example 2 - In Figure 7, above, is a circuit board which contains a μC, FPGA, RAM, flash memory and I/O. Only the μC and FPGA are Bscan compliant. For clarity, the Bscan chain is symbolically indicated with a thick line through these components. The Bscan chain has direct access to the I/O pins of the μC and the FPGA and therefore also to the bus, which contains the address-, data- and control lines. Using the JTAG interface, there is therefore direct access to the connecting pins of, for example, the RAM. To test whether the RAM is connected correctly, special test patterns are shifted into the BSR via the JTAG interface. These test patterns consist of address-, data- and control bits. By choosing appropriate data patterns, data can be written to RAM and it can subsequently be read back.

Based on these results it is possible to determine whether all the pins of the memory chip are connected properly and in the case of a fault, which pin is causing the problem. In a similar manner, it is also possible to program the flash memory.

The data which has to be programmed into flash is integrated into the patterns which are shifted into the BSR. For the testing of the I/O and the connectors this example uses and external Bscan module with a large number of I/O pins.

These pins are connected to the connectors on the board. The BSR of the I/O module is connected in series with the chain on the board (Figure 8). In this way the Bscan has complete access to the connectors and the I/O block on the circuit board and these can be included in the test.

After the board has been tested for any potential manufacturing defects, the JTAG interface is then used to program the software into the internal flash of the μC and to configure the FPGA.

Conclusion

Boundary scan is eminently suitable testing and on-board programming of digital circuit boards. Bscan can also be used in conjunction with non-Bscan components. Since many designs already use Bscan-compliant μCs and CPLD/FPGAs the number of test pads can be greatly reduced.

As a consequence, expensive test fixtures become unnecessary or can be greatly simplified. Thanks to a good diagnosis a problem can be located quickly. Many designers and manufacturing companies recognise these examples and already use Bscan successfully.

For more information please contact Vincent Stafrace using the form below or +61296744222.