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BittWare’s OpenCL Developer’s Bundle | Altera Stratix FPGA-based PCIe

Supplier: Dedicated Systems Australia

BittWare’s OpenCL Developer’s Bundle provides the tools necessary to begin developing applications for the Altera Stratix V using OpenCL.

Price Guide: POA

 OpenCL dramatically simplifies FPGA development by enabling designers to code their systems and algorithms in a high-level C-based framework, directly generating FPGA programming files from a pure software development flow.

The OpenCL Developer’s Bundle includes

BittWare’s S5-PCIe-HQ (S5PH-Q) half-length PCIe board, the BittWorks II system development software, the Altera Quartus II software, and the Altera SDK for OpenCL. This development bundle gives developers access to the latest generation of high-performance FPGAs on a validated COTS PCI Express board, while also significantly reducing their time-to-market by using OpenCL to develop their application.

BittWare’s S5PH-Q is a Gen3, x8 half-size PCIe card based on the high-bandwidth, power-efficient Altera Stratix V FPGA. The S5PH-Q is a versatile and efficient solution for high-performance network processing, signal processing, and data acquisition, with up to 16 GBytes of on-board DDR3 SDRAM and optional QDRII/II+ up to 72 MB (@ 550 MHz). I/O interfaces include two front-panel QSFP+ cages for serial I/O, two SATA connectors, and timestamping support, as well as RS-232, JTAG, and USB for debug.


  • BittWare S5PH-Q Altera Stratix V half-length PCIe board
  • Stratix V GXA7, GXAB, GSD5, or GSD8
  • Two banks of 4 GByte DDR3
  • Four banks of QDRII+ SRAM (optional)
  • Two QSFP+ cages for 40GbE, 10 GbE, or Infiniband
  • S5PH-Q Board Support Package
  • BittWare BittWorks II Toolkit system development software for BittWare COTS boards
  • Altera Quartus® II software
  • Altera Software Development Kit (SDK) for OpenCL

What Are the Benefits of OpenCL for FPGAs?

  • Faster time-to-market using the OpenCL C-based parallel programming language as opposed to low-level hardware description language (HDL)
  • Quick design exploration by working at a higher level of design abstraction
  • Easy design re-use by re-targeting existing OpenCL C code to current and future FPGAs
  • Faster design completion by generating an FPGA implementation of OpenCL C code in a single step, bypassing the manual timing closure efforts and implementation of communication interfaces between the FPGA, host, and external memories.
  • Increased performance by offloading performance-intensive functions from the host processor to the FPGA
  • Significantly lower power by using the Altera SDK for OpenCL which generates only the logic needed to deliver

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